Dr Prashanth B Bhat

MDN-PDM2 Dr. Prashanth B. Bhat
CTO 
Manipal Dot Net Pvt Ltd
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    Dr. Prashanth Bhat is Chief Technology Officer at Manipal Dot Net. He brings over a decade of international quality research, experience and exposure in computer systems and software development. His areas of expertise include Internet search engine technology, parallel and distributed high performance computing, embedded systems, logic design and FPGAs.

    Most recently, he was a Research Engineer at Yahoo! Research, Santa Clara, where he architected some of the key components of Yahoo!'s next generation 'Contextual Match' advertising infrastructure. Prior to this, he worked with Yahoo! India's Advanced Technology Group, developing a distributed systems platform for Machine Learning applications. He has worked on the core technology of Web Search engines for over six years, during his tenures at Yahoo! Inc (USA), Overture Services, and Alta Vista Search. As a summer intern at HP Research Labs, Palo Alto, he developed new process scheduling techniques for HP's high-end parallel servers.
 
    Dr. Prashanth Bhat graduated with a PhD in Computer Engineering from the University of Southern California, Los Angeles, a M. E. in Computer Science and Engineering from the Indian Institute of Science, Bangalore and B. Tech in Computer Engineering from KREC (now NITK) Surathkal. He was awarded the Dr. T.M.A. Pai Gold Medal from Mangalore University. He also secured the 5th rank in the 12th standard, in the state of Karnataka. He won the Best Technical Presentation awards at both graduate and undergraduate levels, and the Best C Programmer award during his undergraduate studies.  

    During his graduate research at USC, he developed analytical models of high performance parallel systems and distributed heterogeneous systems. He proposed new scheduling algorithms for interprocessor communication, using techniques from Operations Research and Shop Scheduling. These models and scheduling techniques were applied towards enhancing the run-time performance of high-end signal processing applications.  

     He holds 2 US patents and has authored about 15 international publications. He served as Industrial Track Chair at the International Parallel and Distributed Processing Symposium (IPDPS) 2001, and has been a reviewer for JPDC, IPPS, ICPP, Proceedings of the IEEE and Supercomputing Conference. He has taught courses in Parallel Computing and Digital Design. He can be reached by Email at prashanth.bhat at manipal.net.